Circuit reliability prediction: Challenges and solutions for the device time-dependent variability characterization roadblock

Copyright IEEEThe characterization of the MOSFET Time-Dependent Variability (TDV) can be a showstopper for reliability-Aware circuit design in advanced CMOS nodes. In this work, a complete MOSFET characterization flow is presented, in the context of a physics-based TDV compact model, that addresses the main TDV characterization challenges for accurate circuit reliability prediction at design time. The pillars of this approach are described and illustrated through examples.This work was supported by the VIGILANT Project (PID2019-103869RB / AEI / 10.13039/501100011033) and the TEC2016-75151-C3-R Project (AEI/FEDER, UE).Peer reviewe

Determination of the Time Constant Distribution of a Defect-Centric Time-Dependent Variability Model for Sub-100-nm FETs

Copyright IEEEThe origin of some time-dependent variability phenomena in FET technologies has been attributed to the charge carrier trapping/detrapping activity of individual defects present in devices. Although some models have been presented to describe these phenomena from the so-called defect-centric perspective, limited attention has been paid to the complex process that goes from the experimental data of the phenomena up to the final construction of the model and all its components, specifically the one that pertains to the time constant distribution. This article presents a detailed strategy aimed at determining the defect time constant distribution, specifically tailored for small area devices, using data obtained from conventional characterization procedures.This work was supported by grants PID2019-103869RB-C31 and PID2019-103869RB-C32 funded by MCIN/AEI/10.13039/501100011033, and by Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía and P.O. FEDER under project US-1380876.Peer reviewe

Unified RTN and BTI statistical compact modeling from a defect-centric perspective

In nowadays deeply scaled CMOS technologies, time-dependent variability effects have become important concerns for analog and digital circuit design. Transistor parameter shifts caused by Bias Temperature Instability and Random Telegraph Noise phenomena can lead to deviations of the circuit performance or even to its fatal failure. In this scenario extensive and accurate device characterization under several test conditions has become an unavoidable step towards trustworthy implementing the stochastic reliability models. In this paper, the statistical distributions of threshold voltage shifts in nanometric CMOS transistors will be studied at near threshold, nominal and accelerated aging conditions. Statistical modelling of RTN and BTI combined effects covering the full voltage range is presented. The results of this work suppose a complete modelling approach of BTI and RTN that can be applied in a wide range of voltages for reliability predictions.Peer reviewe

A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation

copyright IEEEThis paper addresses the automated parameter extraction of Random Telegraph Noise (RTN) models in nanoscale field-effect transistors. Unlike conventional approaches based on complex extraction of current levels and timing of trapping/de-Trapping events from individual defects in current traces, the proposed approach performs a simple processing of current traces. A smart optimization problem formulation allows getting distribution functions of the amplitude of the current shifts and of the number of active defects vs.Time.This work was supported in part by grants PID2019-103869RB-C31 and PID2019-103869RB-C32 funded by MCIN/AEI/ 10.13039/501100011033, and by grant US-1380876 funded by Consejería de Economía, Conocimiento, Empresas y Universidad de la Junta de Andalucía and P.O. FEDER .Peer reviewe

A detailed study of the gate/drain voltage dependence of RTN in bulk pMOS transistors

Random Telegraph Noise (RTN)has attracted increasing interest in the last years. This phenomenon introduces variability in the electrical properties of transistors, in particular in deeply-scaled CMOS technologies, which can cause performance degradation in circuits. In this work, the dependence of RTN parameters, namely current jump amplitude and emission and capture time constants, on the bias conditions, both V and V, has been studied on a set of devices, with a high granularity in a broad voltage range. The results obtained for the V dependences corroborate previous works, but suggest a unique trend for all the devices in a V range that goes from the near-threshold region up to voltages over the nominal operation bias. However, different trends have been observed in the parameters dependence for the case of V. From the experimental data, the probabilities of occupation of the associated defects have been evaluated, pointing out large device-to-device dispersion in the V dependences.Peer Reviewe

Improving the reliability of SRAM-based PUFs under varying operation conditions and aging degradation

The utilization of power-up values in SRAM cells to generate PUF responses for chip identification is a subject of intense study. The cells used for this purpose must be stable, i.e., the cell should always power-up to the same value (either ‘0’ or ‘1’). Otherwise, they would not be suitable for the identification. Some methods have been presented that aim at increasing the reliability of SRAM PUFs by identifying the strongest cells, i.e., the cells that more consistently power-up to the same value. However, these methods present some drawbacks, in terms of either their practical realization or their actual effectiveness in selecting the strongest cells at different scenarios, such as temperature variations or when the circuits have suffered aging-related degradation. In this work, the experimental results obtained for a new method to classify the cells according to their power-up strength are presented and discussed. The method overcomes some of the drawbacks in previously reported methods. In particular, it is experimentally demonstrated that the technique presented in this work outstands in selecting SRAM cells that are very robust against circuit degradation and temperature variations, which ultimately translates into the construction of reliable SRAM-based PUFs.Peer reviewe

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

Copyright IEEETime-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.This work was supported by AEI under Project PID2019-103869RB-C31/AEI/10.13039/501100011033, and by Junta de Andalucia and P.O. FEDER under project US-1380876. Andrés Santana Andreo acknowledges MICINN for supporting his research activity through the predoctoral grant PRE‑2020‑093167.Peer reviewe

A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs

- PUFs based on the power-up values of an array of SRAM cells are a popular solution to provide secure and low-cost key generation suitable for IoT devices. However, SRAM cells do not always power up to the same value due to external factors like noise, temperature, or aging. This results in a decrease of reliability for the SRAM PUF, an issue generally solved by employing complex Error Correction Codes (ECCs). However, ECCs significantly increase the cost of the complete system. A way to alleviate this issue is the use of bit selection methods, which increase the reliability of the SRAM PUF by using only the power-up values of the most reliable cells (i.e., the SRAM cells that consistently power up to the same value). In this work, the reduction in ECC complexity through a bit selection method based on the Data Retention Voltage metric is demonstrated.This work was supported by AEI under Project PID2019-103869RB-C31/AEI/10.13039/501100011033, and by P.O. FEDER under project US-1380876. Pablo Sarazá Canflanca and Andrés Santana Andreo acknowledge MICINN for supporting their research activity through the predoctoral grants BES-2017-080160 and PRE-2020-093167, respectively

A Robust and Automated Methodology for the Analysis of Time-Dependent Variability at Transistor Level

In the past few years, Time-Dependent Variability has become a subject of growing concern in CMOS technologies. In particular, phenomena such as Bias Temperature Instability, Hot-Carrier Injection and Random Telegraph Noise can largely affect circuit reliability. It becomes therefore imperative to develop reliability-aware design tools to mitigate their impact on circuits. To this end, these phenomena must be first accurately characterized and modeled. And, since all these phenomena reveal a stochastic nature for deeply-scaled integration technologies, they must be characterized massively on devices to extract the probability distribution functions associated to their characteristic parameters. In this work, a complete methodology to characterize these phenomena experimentally, and then extract the necessary parameters to construct a Time-Dependent Variability model, is presented. This model can be used by a reliability simulator.Peer reviewe